Inductive wireless power transfer (IPT) and capacitive wireless power transfer (CPT) are currently the two main wireless power transfer technologies. Combining the coils of the IPT with the plates of the CPT creates a hybrid wireless power transfer (HPT) system, which can improve the transmission performance but introduces higher parameter sensitivity. Therefore, achieving stable output power and constant transfer efficiency over a wide range of coupling coefficient variations is still a major challenge for HPT. In this work, the parity-time (PT) symmetry theory is applied to an SS-type HPT system, and a circuit model of the PT-based HPT system is developed by using coupling capacitance and coupling inductance. The effect of connecting the plates to the homonymous end or heteronymous end of the coupling coils on the PT-symmetry range of the HPT system is discussed. It is found that the heteronymous end connection of the coils can effectively increase the range of constant output power and stable transfer efficiency. Finally, a prototype is built to verify the feasibility and effectiveness of the proposed PT-based HPT system. The transfer efficiency remains constant in the PT-symmetric range, and the inductive and capacitive coupling coefficients are smaller compared to IPT and CPT systems with the same parameters.

As the increasing demands for the constant voltage (CV) charging of multiple loads, this article proposes an LC compensated wireless power transfer (WPT) system with multiple CV outputs function. The proposed WPT system can achieve multiple voltage outputs without decoupling method. Each voltage output channel is composed of a compensation capacitor and a compensation inductor connected in series. By configuring different compensation inductors and capacitors for each output channel, it can achieve different CV outputs without affecting the output voltage of other output channels. In addition, the system can achieve near-zero phase angle (ZPA) and zero-voltage switching (ZVS) operations, which can improve system efficiency. Finally, the correctness and rationality of the proposed WPT system is verified by built an experimental prototype with two CV output channels.

This paper proposes a readout scheme that utilizes a pair of differential-clocks-assisted time-to-digital converter (DCA-TDC) in CMOS image sensors (CISs). The DCA-TDC utilizes only half the number of ordinary TDC delay chain units by employing a binary-weighted search algorithm to determine the most significant bit (MSB) for fine quantization of a single-slope analog-to-digital converter (SSADC). The layout area and dynamic power introduced by the improved DCA-TDC delay chain are reduced by half compared to an ordinary TDC delay chain. The proposed SS ADC is designed and simulated using the 0.11 µm standard CMOS process. In the design environment with an analog voltage of 3.3 V, a digital voltage of 1.5 V, a clock frequency of 62.5 MHz, and a temporal resolution of 500 ps, this design is an 11-bit ADC with column-level power consumption of 65.4 µW, a row conversion time of 2.72 µs. Furthermore, it achieves an effective number of bits (ENOB) of 10.75 and a figure-of-merit (FoM) of 103.3 fJ/step. By interpolating a DCA-TDC, the quantization speed is faster than a traditional SS ADC. This scheme offers an effective solution for implementing high-frame-rate CISs.

Accurate estimation of lithium-ion battery state of energy (SOE) is an important prerequisite for prolonging battery life and ensuring battery safety. To achieve a high-precision estimation of SOE, this study focuses on ternary lithium-ion batteries and proposes an SOE estimation method that combines limited-memory recursive least squares (LM-RLS) with strong tracking adaptive window Multi-innovation cubature Kalman filtering (STF-MCKF). A finite set of data is used for model parameter updates at the current time to solve the problem of data saturation and improve the identification accuracy of the RLS algorithm. By utilizing the STF algorithm, the CKF algorithm is optimized to enhance its robustness under strong disturbances. An adaptive window Multi-innovation strategy is proposed to improve the accuracy of SOE estimation and the stability of the CKF algorithm while maintaining a balance between computational complexity and estimation accuracy. To validate the effectiveness of the algorithm, experiments are conducted under DST and BBDST conditions. The results show that the STF-MCKF algorithm has a maximum convergence time of 4s and an SOE estimation error within 1.04% under DST conditions. Under BBDST conditions, the STF-MCKF algorithm has a maximum convergence time of 3s and an SOE estimation error within 2.34%. Furthermore, the STF-MCKF algorithm demonstrates good stability under both the two conditions, indicating the effectiveness of the proposed improved algorithm for lithium battery SOE estimation.

In this study, we investigated a new structure of a protective meander line (ML): a meander microstrip line (MSL) with two passive conductors. The existing theory of ultra-short pulse (USP) attenuation in MLs is presented for the first time. Based on this theory, we determined the number of decomposed pulses at the output of the MSL line with two passive conductors, and, for the first time, formulated the conditions for pulse decomposition in the line. The folding of the MSL line into non-core turns was studied in detail. As a result of this study, we proposed a new theory that involves the utilization of additional groups of decomposed pulses for enhanced USP attenuation. These additional groups were thoroughly examined, and the delays of pulses from these groups were defined. This analysis allowed identifying the reason for their appearance. It was revealed that folding the meander line into non-core turns allows further attenuation of the USP amplitude, which increases with the increase of the number of non-core turns. To validate the obtained simulation results, we performed experimental measurements and obtained good consistency of the results. The N-norms analysis demonstrated that combined use of such folding and passive conductors reduces the probability of electrical breakdown, arc discharge, and dielectric breakdown. The maximum USP attenuation at the output was 24.9 dB. As a result of useful signal integrity analysis, it is proposed to use a folded meander microstrip line (MSL) together with a USB 2.0 “Full-speed” interface with a data transfer rate of 12 Mbit/s. In addition, it is proposed to use such MSLs in DC power circuits.

This research introduces a Power Harmonics Suppression (Damping) based generation of reference currents for reliable operation of DFIGs with harmonic distortion in grid voltage. The imbalances and dominant harmonic components (negative sequence as well as 5 th and 7 th harmonics) in the grid voltage, induces stator active and reactive power oscillations of 200Hz, 300Hz, 400Hz and 600Hz. Further this lead to braking & forward torque and unreliable performance of DFIG aiding to grid instability issues. Thus, a modified set of current references are created for the d-q axes current control and these references are designed to reduce the imbalances and harmonics in electromagnetic torque, as well as stator active and reactive power, with a single objective of damping power oscillations. Simultaneously, the GSC is focused on mitigating fluctuations in the DC- link voltage while enabling UPF operation on the grid side. The novel current references for RSC and GSC are derived by incorporating negative sequence as well as 5 th and 7 th harmonic compensating currents along with the steady state current references, to acquire the desired targets. The overall system is validated with PSCAD/EMTDC simulations and using OPAL-RT OP4510 real-time simulator, on a 2.3kVA DFIG.

Multi module isolated converters (MMICs) find extensive application in various DC-DC applications due to their remarkable features of galvanic isolation, bi-directional power flow, high power density and enhanced efficiency. However, voltage and current sharing among the converter modules are the most significant issues in MMICs. This paper proposes Multi-port Integrated-Magnetics Transformers (MpIMTs) which address the input-output DC-link voltage imbalances within an ISOS converter. The proposed transformers ensure the input voltage sharing (IVS) and output voltage sharing (OVS) through balancing windings within their structures, thus substitutes the complicated active control scheme with the balancing winding. Besides, the input side and output side modules are decoupled from each other, thus the impact of parameters variation and inter-module energy transfer during a transient of one side does not reflect to the other side. These properties are achieved by proposing a custom-designed core and an off the shelf available U core assembled MpIMTs. The magnetic and electrical equivalent along with the design criteria of the balancing winding are also presented. Furthermore, the paper includes the comparative analysis of the proposed transformers which reveals that while the U-core MpIMT offers simplified construction, it comes at the expense of slightly reduced efficiency compared to the custom-designed MpIMT. Finally, the proposed U core MpIMT is validated through a laboratory prototype.

The detection of high voltage permanent magnet motors has always been a big problem due to the interference of high voltage and magnetic field on the diagnosis. Especially the magenetic tile of the motor, the failure of the magenetic tile will directly lead to the operation failure of the motor. We propose Multi-view Unsupervised Consistent Soft-label Feature Selection(MUCSFS). This method constructed consistent pseudo-labels through soft labels of clustering affinity of each view sample and constructed the model by integrating selection constraints into the mapping model. This model is used to filter the fault data set to get the feature subset, and the feature subset is used to cluster. We verify the effectiveness of the method by simulating multi-view data and through the fault clustering experiment of the magnetic tile fault data set of high voltage motor, it is confirmed that our method can effectively cluster the fault categories.

The present study is devoted to articulating a modified Folded-Cascode circuit, to make Folded-Cascode structures an attractive configuration as a Transimpedance Amplifier (TIA) for being employed in Giga-bit per second optical communication receiver systems. Giga-bps communication receivers are highly necessitating circuits to isolate the input parasitic capacitance of the photodiode. The present modification makes Folded Cascodes comparable to the famous Regulated Cascode (RGC) structures by isolating this parasitic capacitor almost by the same quantity. The system is shown to be capable of operating at 2.5Gbps up to 8Gbps data rate with a fixed bandwidth. The paper analyzes and evaluates the designed circuit mathematically, and the obtained simulated results from Cadence using TSMC 65nm CMOS validate the suitability of the modified circuit as a transimpedance amplifier.

This paper presents a compact CMOS tunable positive and negative active inductor simulator (AIs), positive capacitance and resistance multiplier and negative capacitance and resistance simulator. The proposed design use only one analog building block (ABB) and three passive elements. Applications in the design of different types of tunable filters and parasitic compensation are also presented. The functionality of the design is confirmed using Tanner Tspice in 0.18µm TSMC CMOS technology. Simulation results indicate that the proposed design is superior to previous arts in many aspects.

By multiplying with the continuous factor (CF), the conventional Class- F / F - 1 , Class-J power amplifier (PA) can be expanded to their corresponding continuous modes, resulting in a great degree of freedom for broadband design. However, this method can hardly apply to other types of PAs. In view of this problem, the continuous mode is deeply analyzed from the perspective of equation solving for the first time, and a general theory for high-efficiency broadband continuous PA design is proposed. In this theory, the continuous impedance space does not rely on a mapping relationship achieved by multiplying with the CF, but on a direct solution of the high-efficiency equations to obtain the broadband design space. This approach is simpler and has the potential to provide greater design space. As a validation, this theory is used for the analysis of Class-E PAs and a new continuous Class-E (NC-E) PA is presented. With knee-point voltage and finite harmonics taken into account, this type of PA greatly expands the broadband design space of Class-E PAs, and also has the advantage of harmonic matching. The NC-E PA is designed and manufactured using GaN HEMT CGH40010F, which achieves 40.6∼41.6dBm output power and 66.2%∼74.2% drain efficiency (DE) in the frequency band of 2.5-3.8GHz.

Variable supply voltage-clustered voltage scaling (VS-CVS) is an effective way to decrease power consumption without compromising performance. One of the major challenges in VS-CVS design is that level converting flip-flops(LCFFs) not only need to have low power consumption but also high performance. In this paper, we propose two new structures of LCFF: the data branch sharing LCFF based on conditional charging (DBS-LCFFCC) and the data branch sharing LCFF based on precharging (DBS-LCFFP).The new structures adopt a data branch sharing scheme to improve the speed of the circuit as well as to reduce the number of transistors. Based on simulation results using HSPICE with PTM 32nm CMOS technology, the proposed LCFFs show an improvement of 19.2% to 67.2% and 41.6% to 76.3% in power-delay-product (PDP) at 50% data switching activity, respectively, compared to other advanced LCFFs.

In this paper, for standalone and grid-connected PV systems, a three-phase simplified split-source inverter (SSI) is proposed and controlled using a model-predictive control (MPC). The maximum power point tracking (MPPT) approach used is an incremental conductance method based on a PI controller for both systems. The standalone system is composed of PV modules, a three-phase SSI, and a bidirectional power DC-DC converter that connects a battery bank and a DC-side capacitor. The output AC voltages of SSI are controlled using model-predictive control. The bidirectional power DC/DC converter regulates the DC-link voltage (DCLV). The grid-connected system consists of PV modules, a three-phase SSI, and an AC-side L-filter. The DC-link PI controller generates reference currents for the MPC algorithm. The MPC uses these reference currents to adjust and deliver the PV power to the grid while regulating the DCLV. The PI controllers’ parameters are selected for both systems using the Harris Hawks optimization method. Both PV systems simulation results show that under various operating conditions, they have succeeded in fixing a DCLV and producing a high-quality AC output voltage and current at low THD. Experimental results for the three-phase standalone PV system used to verify the system’s performance.

Summary: This paper proposes a 1/f noise optimized correlated multiple sampling (NOCMS) technique based on differentiated sampling weights for CMOS image sensor. Transfer functions of standard CMS and NOCMS for analyzing the suppression effect of random noise respectively are derived based on the Fourier Transform theory. NOCMS shows a dramatic advantage in the suppression of 1/f noise. For implementing NOCMS, the ramp generator provides multiple sets of ramps with different slopes to quantize the reset and signal voltages. Sampling weights are increased with the decrease of ramp slopes. The last reset and first signal values are weighted more due to their potentially higher correlations. Simulation results under 110nm CMOS technology illustrate that the ADC achieves DNL of −0.80/+0.70LSB and INL of −0.70/+0.90LSB after the NOCMS operation. The input-referred random noise is 142.9µV rms under standard CMS and 120.9µV rms under NOCMS when the number of samples equals 8. The noise reduction effect is improved by 15%. NOCMS makes it possible to further reduce 1/f noise of CMOS image sensor.

Bipolar junction transistors (BJTs) are widely used in various electronic systems, and the establishment of the electromagnetic compatibility (EMC) model for BJTs is crucial for EMC analysis of these systems, such as high-frequency circuits. In this paper, a BJT EMC model that satisfies both functionality and EMC analysis requirements was established based on physical characteristic measurement. Firstly, comprehensive and systematic methods for measurement and extracting SPICE parameters based on physical BJTs are presented, including a proposed curve-fitting calculation method for extracting barrier capacitance parameters. Secondly, an analysis of the impact of major BJT electrical characteristics parameters was conducted, leading to the identification of important model parameters affecting BJT functionality and EMC. Finally, the primary BJT model was optimized using the simplex method, and a method for EMC analysis and verification of the BJT model was presented. The experimental and simulation results are in good agreement, and the established model meets the accuracy requirements for both EMC and functionality. Therefore, the proposed method is feasible and suitable for the EMC modeling of BJTs.

Systems with non-Hermitian Hamiltonians, especially those exhibiting parity-time ( PT ) symmetry, are of particular interest as they can describe physical open systems with balanced loss into and gain from the environment. In this context, the study of eigenvalue locations and the corresponding phase transitions as a function of the degree of non-Hermiticity γ is accomplished hereby using feedback theory. This approach provides insight about the behavior of these systems and allows generalization of the results for higher-order ones. The proposed ideas are analyzed in detail for a class of coupled resonant circuit chains.

In this paper, a noteworthy compact dual band wireless power transfer (DB-WPT) system is presented and studied. This system is proposed using interdigital capacitor which reduced the size of the whole system and accomplished high efficiencies. An interdigital capacitor is printed in the ground plane of the design and loaded with a chip capacitor to produce dual bands. The operation of the system is verified by fabricating the proposed DB-WPT system, which shows measured coupling efficiencies of 96 % and 98.8 % at 0.53 and 1.1 GHz, respectively at a transfer space of 12 mm. The fabricated structure has dimensions of 13.5 mm × 20 mm. The results show good agreement between the circuit model and the measurements. The idea of this design makes it applicable for compact near field WPT applications.

A novel transformerless three-phase unidirectional bridgeless flying capacitor (UBFC) rectifier for medium-voltage and high-voltage applications is presented by this paper. The rectifier consists of three single-phase rectifiers in wye connection, the DC outputs of the three single-phase rectifiers are connected in parallel to provide a high common DC-link bus which makes it convenient to connect with NPC or FC multilevel inverters. To avoid phase to phase current circulation, an additional inductor and diode are added to each single-phase rectifier. Compared with conventional bidirectional multilevel converters, only half IGBTs are employed with lower voltage stress, line-frequency transformers are no longer be required, which makes the proposed rectifier has a series of advantages such as reduced cost, simplified control complexity, increased reliability and improved overall efficiency. The basic operating principle of the proposed rectifier in continuous conduction mode is discussed, an improved carrier-based level-shifted PWM modulation method integrated with voltage balancing and the double closed-loop control strategy are proposed to achieve more voltage levels and keep the flying capacitors in balance. The feasibility of proposed rectifier is verified by the simulation as well as experimental results.