(e) (f)
Fig. 10. PVT variations effect on the LCFFs’ performances: (a)
process corners vs. power, (b) process corners vs. delay, (c) voltage
vs. power, (d) voltage vs. delay, (e) temperature vs. power, (f)
temperature vs. delay.
Conclusion
In this paper, we propose two types of double-edge pulse level
conversion flip-flops based on data branch sharing , which can
effectively reduce the number of transistors in the charge/discharge
path and subsequently decrease the delay and area of the circuit. Among
them, the DBS-LCFFCC employs the conditional charging technique to
further decrease power consumption, while the DBS-LCFFP employs the
precharging technique to further reduce delay. Simulation results show
that both the proposed level-conversion flip-flops have lower power
consumption and delay comparedto the existing level-conversion
flip-flops.
Acknowledgments
This work was supported by the Basic Public Welfare Research Program of
Zhejiang Province under Grant LTGY23H170004.
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