(a) (b)
Fig. 2. (a) Clock pulse generator; (b) Double-edge triggered level converter flip-flop with feedback (LCFFF).
Fig. 3 shows the novel dynamic explicit-pulsed double edge triggered level converting flip-flop (nEP-DET-LCFF) [11], which removes the redundant switching activity of node X by using conditional discharge techniques to reduce the dynamic power consumption. However, the circuit’s maximum NMOS transistor stack of 3, results in a long discharge branch for node X,, leading to a significant circuit delay. Moreover, the nEP-DET-LCFF requires more transistors than other designs, which increases the power consumption and area overhead.
The level converting flip-flop based on pass-transistor logic (LCFFBPT) [12] is shown in Fig. 4, which employs the feedback devices MP1 and MP3 to reduce the capacitive load (gate capacitance of the keeper device) at node V. However, when the input signal D changes from high to low during the presence of the pulse, the pull-up and pull-down branches of node V turn on simultaneously. Therefore, the pull-down branch needs to be strong enough to overcome the pull-up branch, which increases the power consumption and delay of the flip-flop.